Linear Time-Periodic Modeling, Examination, and Performance Enhancement of Grid Synchronization Systems With DC Component Rejection/Estimation Capability

The dc component, which may be caused by different factors in the grid voltage, is one of disturbances that severely affect performance synchronization systems and, therefore, grid-tied power converters. In phase-locked loop (PLL) and frequency-locked (FLL)-based systems, this article focuses on, some solutions to deal with challenge have been proposed literature. One best available adding rejection/estimation loop(s) a standard PLL FLL structure. This approach provides an estimation component at same time, makes immune disturbance effects component. Despite their implementation simplicity, no linear model for capability has yet presented. main aim fill research gap. It will shown developing such models facilitates examination enhancement under study.